PIC18F83J11T-I/PT【PDF 5/332 页】IC PIC MCU FLASH 4KX16 80TQFP

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PIC18F85J11 FAMILY

DS39774D-page 102

2010 Microchip Technology Inc.

8.3

Wait States

While it may be assumed that external memory devices

will operate at the microcontroller clock rate, this is

often not the case. In fact, many devices require longer

times to write or retrieve data than the time allowed by

the execution of table read or table write operations.

To compensate for this, the external memory bus can

be configured to add a fixed delay to each table opera-

tion using the bus. Wait states are enabled by setting

the WAIT Configuration bit. When enabled, the amount

of delay is set by the WAIT<1:0> bits (MEMCON<5:4>).

The delay is based on multiples of microcontroller

instruction cycle time and are added following the

instruction cycle when the table operation is executed.

The range is from no delay to 3 TCY (default value).

8.4

Port Pin Weak Pull-ups

With the exception of the upper address lines,

A<19:16>, the pins associated with the external mem-

ory bus are equipped with weak pull-ups. The pull-ups

are controlled by the upper three bits of the PORTG

control pull-ups on PORTD, PORTE and PORTJ,

respectively. Setting one of these bits enables the

corresponding pull-ups for that port. All pull-ups are

disabled by default on all device Resets.

8.5

Program Memory Modes and the

External Memory Bus

The PIC18F85J11 family of devices are capable of

operating in one of two Program Memory modes, using

combinations of on-chip and external program memory.

The functions of the multiplexed port pins depend on

the Program Memory mode selected, as well as the

setting of the EBDIS bit.

In Microcontroller Mode, the bus is not active and the

pins have their port functions only. Writes to the

MEMCOM register are not permitted. The Reset value

of EBDIS (‘0’) is ignored and EMB pins behave as I/O

ports.

In Extended Microcontroller Mode, the external

program memory bus shares I/O port functions on the

pins. When the device is fetching or doing table

read/table write operations on the external program

memory space, the pins will have the external bus

function.

If the device is fetching and accessing internal program

memory locations only, the EBDIS control bit will

change the pins from external memory to I/O port

functions. When EBDIS = 0, the pins function as the

external bus. When EBDIS = 1, the pins function as I/O

ports.

If the device fetches or accesses external memory

while EBDIS = 1, the pins will switch to the external

bus. If the EBDIS bit is set by a program executing from

external memory, the action of setting the bit will be

delayed until the program branches into the internal

memory. At that time, the pins will change from external

bus to I/O ports.

If the device is executing out of internal memory when

EBDIS = 0, the memory bus address/data and control

pins will not be active. They will go to a state where the

active address/data pins are tri-state; the CE, OE,

WRH, WRL, UB and LB signals are ‘1’ and ALE and

BA0 are ‘0’. Note that only those pins associated with

the current address width are forced to tri-state; the

other pins continue to function as I/O. In the case of

16-bit address width, for example, only AD<15:0>

(PORTD and PORTE) are affected; A<19:16>

(PORTH<3:0>) continue to function as I/O.

In all External Memory modes, the bus takes priority

over any other peripherals that may share pins with it.

This includes the Parallel Slave Port and serial commu-

nication modules which would otherwise take priority

over the I/O port.

8.6

16-Bit Data Width Modes

In 16-Bit Data Width mode, the external memory

interface can be connected to external memories in

three different configurations:

16-Bit Byte Write

16-Bit Word Write

16-Bit Byte Select

The configuration to be used is determined by the

WM<1:0>

bits

the

MEMCON

(MEMCON<1:0>). These three different configurations

allow the designer maximum flexibility in using both

8-bit and 16-bit devices with 16-bit data.

For all 16-Bit Data Width modes, the Address Latch

Enable (ALE) pin indicates that the address bits,

AD<15:0>, are available on the external memory inter-

face bus. Following the address latch, the Output

Enable signal (OE) will enable both bytes of program

memory at once to form a 16-bit instruction word. The

Chip Enable signal (CE) is active at any time that the

microcontroller accesses external memory, whether

reading or writing. It is inactive (asserted high)

whenever the device is in Sleep mode.

In Byte Select mode, JEDEC standard Flash memories

will require BA0 for the byte address line and one I/O

line to select between Byte and Word mode. The other

16-Bit Data Width modes do not need BA0. JEDEC

standard static RAM memories will use the UB or LB

signals for byte selection.

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